1427 search results - page 14 / 286 » Achieving High Performance with FPGA-Based Computing |
123
click to vote
CLUSTER
2006
IEEE
15 years 10 months ago
2006
IEEE
As new processor and memory architectures advance, clusters start to be built from larger SMP systems, which makes MPI intra-node communication a critical issue in high performanc...
131
click to vote
CCGRID
2006
IEEE
15 years 7 months ago
2006
IEEE
MPICH2 provides a layered architecture for implementing MPI-2. In this paper, we provide a new design for implementing MPI-2 over InfiniBand by extending the MPICH2 ADI3 layer. Ou...
119
click to vote
DAC
1996
ACM
15 years 8 months ago
1996
ACM
: In a high performance microprocessor such as Digital's 300MHz Alpha 21164, the distribution of a high quality clock signal to all regions of the device is achieved using a c...
163
click to vote
SBACPAD
2008
IEEE
15 years 10 months ago
2008
IEEE
This work presents an implementation of Neocognitron Neural Network, using a high performance computing architecture based on GPU (Graphics Processing Unit). Neocognitron is an ar...
121
click to vote
PPOPP
1995
ACM
15 years 7 months ago
1995
ACM
Scalable busy-wait synchronization algorithms are essential for achieving good parallel program performance on large scale multiprocessors. Such algorithms include mutual exclusio...