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» Activity-driven clock design for low power circuits
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DATE
2008
IEEE
157views Hardware» more  DATE 2008»
15 years 6 months ago
Clock Distribution Scheme using Coplanar Transmission Lines
The current work describes a new standing wave oscillator scheme aimed for clock propagation on coplanar transmission lines on a silicon die. The design is aimed for clock signali...
Victor H. Cordero, Sunil P. Khatri
DFT
2006
IEEE
122views VLSI» more  DFT 2006»
15 years 3 months ago
Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) Design
The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synch...
Minsu Choi, Myungsu Choi, Zachary D. Patitz, Nohpi...
ISQED
2005
IEEE
99views Hardware» more  ISQED 2005»
15 years 5 months ago
Design Considerations for Low-Power Ultra Wideband Receivers
Abstract - This paper studies design considerations for lowpower ultra wideband (UWB) receiver architectures. First, three different architectures for the impulse-radio UWB transce...
Payam Heydari
ISVLSI
2006
IEEE
106views VLSI» more  ISVLSI 2006»
15 years 5 months ago
Self-Timed Thermally-Aware Circuits
Thermal management is becoming increasingly important in circuit designs with high power density. Circuits that overheat beyond specified operating conditions may suffer timing f...
David Fang, Filipp Akopyan, Rajit Manohar
ISLPED
2006
ACM
122views Hardware» more  ISLPED 2006»
15 years 5 months ago
Dynamic thermal clock skew compensation using tunable delay buffers
—The thermal gradients existing in high-performance circuits may significantly affect their timing behavior, in particular, by increasing the skew of the clock net and/or alteri...
Ashutosh Chakraborty, Karthik Duraisami, Ashoka Vi...