433 search results - page 50 / 87 » Activity-driven clock design for low power circuits |
102
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ASPDAC
2009
ACM
15 years 6 months ago
2009
ACM
— In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in two-dimensional (2D) designs. Therefore, the power supply noise pro...
111
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ISPD
2005
ACM
15 years 7 months ago
2005
ACM
In the nanometer VLSI technology, the variation effects like manufacturing variation, power supply noise, temperature etc. become very significant. As one of the most vital nets...
133
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FPGA
2009
ACM
15 years 8 months ago
2009
ACM
Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA’s lo...
100
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VLSID
1999
IEEE
15 years 6 months ago
1999
IEEE
This paper provides a theoretical basis for eliminating or reducing the energy consumption due to transients in a synchronous digital circuit. The transient energy is minimized wh...
FPGA
2005
ACM
15 years 7 months ago
2005
ACM
Modern FPGA architectures provide ample routing resources so that designs can be routed successfully. The routing architecture is designed to handle versatile connection configur...