433 search results - page 9 / 87 » Activity-driven clock design for low power circuits |
FPGA
2009
ACM
15 years 6 months ago
2009
ACM
Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R VirtexTM -5 FPGA are presen...
93
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ISVLSI
2007
IEEE
15 years 6 months ago
2007
IEEE
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
FPGA
2006
ACM
15 years 3 months ago
2006
ACM
This paper examines the tradeoffs between flexibility, area, and power dissipation of programmable clock networks for FieldProgrammable Gate Arrays (FPGA's). The paper begins...
113
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ISCAS
2007
IEEE
15 years 5 months ago
2007
IEEE
Abstract—This paper presents a low power 4-bit ADC for subGHz Ultra Wideband (UWB) receivers. The power efficiency is achieved by taking advantage of the low duty cycle feature o...
74
Voted
ISPD
2006
ACM
15 years 5 months ago
2006
ACM
The integration of retiming and simultaneous supply/threshold voltage scaling has a potential to enable more rigorous total power reduction. However, such integration is a highly ...