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» Adaptive Aggregation on Chip Multiprocessors
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MICRO
2008
IEEE
116views Hardware» more  MICRO 2008»
15 years 11 months ago
Power reduction of CMP communication networks via RF-interconnects
As chip multiprocessors scale to a greater number of processing cores, on-chip interconnection networks will experience dramatic increases in both bandwidth demand and power dissi...
M.-C. Frank Chang, Jason Cong, Adam Kaplan, Chunyu...
156
Voted
IPPS
2007
IEEE
15 years 11 months ago
Virtual Execution Environments: Support and Tools
In today’s dynamic computing environments, the available resources and even underlying computation engine can change during the execution of a program. Additionally, current tre...
Apala Guha, Jason Hiser, Naveen Kumar, Jing Yang, ...
ICS
2010
Tsinghua U.
15 years 7 months ago
The auction: optimizing banks usage in Non-Uniform Cache Architectures
The growing influence of wire delay in cache design has meant that access latencies to last-level cache banks are no longer constant. Non-Uniform Cache Architectures (NUCAs) have ...
Javier Lira, Carlos Molina, Antonio Gonzále...
CASES
2005
ACM
15 years 7 months ago
Software-directed power-aware interconnection networks
Interconnection networks have been deployed as the communication fabric in a wide range of parallel computer systems. With recent technological trends allowing growing quantities ...
Vassos Soteriou, Noel Eisley, Li-Shiuan Peh
IWMM
2010
Springer
118views Hardware» more  IWMM 2010»
15 years 10 months ago
Speculative parallelization using state separation and multiple value prediction
With the availability of chip multiprocessor (CMP) and simultaneous multithreading (SMT) machines, extracting thread level parallelism from a sequential program has become crucial...
Chen Tian, Min Feng, Rajiv Gupta