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ASPLOS
2011
ACM
14 years 3 months ago
Inter-core prefetching for multicore processors using migrating helper threads
Multicore processors have become ubiquitous in today’s systems, but exploiting the parallelism they offer remains difficult, especially for legacy application and applications ...
Md Kamruzzaman, Steven Swanson, Dean M. Tullsen
DAC
2009
ACM
16 years 25 days ago
Process variation characterization of chip-level multiprocessors
Within-die variation in leakage power consumption is substantial and increasing for chip-level multiprocessors (CMPs) and multiprocessor systems-on-chip. Dealing with this problem...
Lide Zhang, Lan S. Bai, Robert P. Dick, Li Shang, ...
DSN
2007
IEEE
15 years 6 months ago
BlackJack: Hard Error Detection with Redundant Threads on SMT
Testing is a difficult process that becomes more difficult with scaling. With smaller and faster devices, tolerance for errors shrinks and devices may act correctly under certain ...
Ethan Schuchman, T. N. Vijaykumar
SBACPAD
2007
IEEE
130views Hardware» more  SBACPAD 2007»
15 years 6 months ago
Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)
In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-Multi Processor (CMP). It adopts a wormhole switc...
Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh
ICPP
2008
IEEE
15 years 6 months ago
Optimizing Issue Queue Reliability to Soft Errors on Simultaneous Multithreaded Architectures
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
Xin Fu, Wangyuan Zhang, Tao Li, José A. B. ...