25 search results - page 2 / 5 » Address Bus Encoding Techniques for System-Level Power Optim... |
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CODES
2004
IEEE
15 years 1 months ago
2004
IEEE
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
CASES
2003
ACM
15 years 2 months ago
2003
ACM
Reducing the power consumption of computing devices has gained a lot of attention recently. Many research works have focused on reducing power consumption in the off-chip buses as...
TVLSI
2002
14 years 9 months ago
2002
This paper presents an irredundant encoding technique to minimize the switching activity on a multiplexed Dynamic RAM (DRAM) address bus. The DRAM switching activity can be classif...
DAC
2000
ACM
15 years 10 months ago
2000
ACM
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...
51
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ASPDAC
2004
ACM
15 years 3 months ago
2004
ACM
— In deep-submicron (DSM) technology, minimizing power consumption of a bus is one of the most important design objectives in embedded system-on-chip (SoC) design. In this paper,...