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» Address Code Generation for Digital Signal Processors
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LCPC
2007
Springer
15 years 5 months ago
A Novel Asynchronous Software Cache Implementation for the Cell-BE Processor
This paper describes the implementation of a runtime library for asynchronous communication in the Cell BE processor. The runtime library implementation provides with several servi...
Jairo Balart, Marc González, Xavier Martore...
MICRO
2007
IEEE
164views Hardware» more  MICRO 2007»
15 years 5 months ago
A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs
The emergence of multicore processors has heightened the need for effective parallel programming practices. In addition to writing new parallel programs, the next generation of pr...
William Thies, Vikram Chandrasekhar, Saman P. Amar...
DFT
2004
IEEE
95views VLSI» more  DFT 2004»
15 years 3 months ago
Mixed Loopback BiST for RF Digital Transceivers
In this paper we analyze the performance of a mixed built-in-self-test (BiST) for RF IC digital transceivers, where a baseband processor can be used both as a test pattern generat...
Jerzy Dabrowski, Javier Gonzalez Bayon
ASPDAC
2004
ACM
120views Hardware» more  ASPDAC 2004»
15 years 5 months ago
Compiler based exploration of DSP energy savings by SIMD operations
— The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting their special architecture features. Beside the ...
Markus Lorenz, Peter Marwedel, Thorsten Dräge...
PC
2006
124views Management» more  PC 2006»
14 years 11 months ago
Message-passing code generation for non-rectangular tiling transformations
Tiling is a well known loop transformation used to reduce communication overhead in distributed memory machines. Although a lot of theoretical research has been done concerning th...
Georgios I. Goumas, Nikolaos Drosinos, Maria Athan...