1108 search results - page 73 / 222 » Algorithm Transformation for FPGA Implementation |
ISCAS
1999
IEEE
15 years 6 months ago
1999
IEEE
The SOVA and the log-MAP are commonly used in turbo decoding. In this paper, we propose to modify the sliding window MAP-algorithm in [5]to reduce the computational delay even fur...
IFIP
1999
Springer
15 years 6 months ago
1999
Springer
: This paper presents a synthesis algorithm for pipelined circuits. The circuit is specified as a collection of independent, looselycoupled modules connected by queues. The synthe...
132
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FPL
2008
Springer
15 years 3 months ago
2008
Springer
The phase detector is a main building block in phaselocked loop (PLL) applications. FPGAs permit the realtime implementation of the CORDIC algorithm which offers an efficient solu...
128
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FPL
2010
Springer
14 years 12 months ago
2010
Springer
Abstract--Modular multiplication of long integers is an important building block for cryptographic algorithms. Although several FPGA accelerators have been proposed for large modul...
IPPS
2007
IEEE
15 years 8 months ago
2007
IEEE
This paper explores the correlation of instruction counts and cache misses to runtime performance for a large family of divide and conquer algorithms to compute the Walsh–Hadama...