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DATE
1999
IEEE
147views Hardware» more  DATE 1999»
15 years 9 months ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi
CL
2007
Springer
15 years 5 months ago
A bulk-synchronous parallel process algebra
The CCS (Calculus of Communicating Systems) process algebra is a well-known formal model of synchronization and communication. It is used for the analysis of safety and liveness i...
Armelle Merlin, Gaétan Hains
PPOPP
2011
ACM
14 years 8 months ago
Cooperative reasoning for preemptive execution
We propose a cooperative methodology for multithreaded software, where threads use traditional synchronization idioms such as locks, but additionally document each point of potent...
Jaeheon Yi, Caitlin Sadowski, Cormac Flanagan
RTSS
2009
IEEE
15 years 11 months ago
Spatiotemporal Delay Control for Low-Duty-Cycle Sensor Networks
—Data delivery is a major function of sensor network applications. Many applications, such as military surveillance, require the detection of interested events to be reported to ...
Yu Gu, Tian He, Mingen Lin, Jinhui Xu
MSWIM
2005
ACM
15 years 10 months ago
Topology control with better radio models: implications for energy and multi-hop interference
Topology Control (TC) is a well-studied technique used in wireless ad hoc networks to find energy-efficient and/or low-interference subgraphs of the maxpower communication graph....
Douglas M. Blough, Mauro Leoncini, Giovanni Resta,...