3456 search results - page 96 / 692 » Algorithms for Interface Synthesis |
116
Voted
TVLSI
2010
14 years 9 months ago
2010
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...
109
Voted
FPGA
2009
ACM
15 years 9 months ago
2009
ACM
Reconfigurable high-performance computing systems (RHPC) have been attracting more and more attention over the past few years. RHPC systems are a promising solution for accelerati...
111
Voted
ISPD
2003
ACM
15 years 8 months ago
2003
ACM
For multi-gigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register ...
130
Voted
DATE
1999
IEEE
15 years 7 months ago
1999
IEEE
In this paper, we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrate...
117
Voted
CEC
2007
IEEE
15 years 4 months ago
2007
IEEE
Abstract—The high-level synthesis process allows the automatic design and implementation of digital circuits starting from a behavioral description. Evolutionary algorithms are v...