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144
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DAC
2006
ACM
16 years 3 months ago
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
Yu Hu, Yan Lin, Lei He, Tim Tuan
112
Voted
STOC
2002
ACM
149views Algorithms» more  STOC 2002»
16 years 2 months ago
The complexity of choosing an H-colouring (nearly) uniformly at random
Cooper, Dyer and Frieze studied the problem of sampling H-colourings (nearly) uniformly at random. Special cases of this problem include sampling colourings and independent sets a...
Leslie Ann Goldberg, Steven Kelk, Mike Paterson
150
Voted
TPCD
1994
157views Hardware» more  TPCD 1994»
15 years 3 months ago
Non-Restoring Integer Square Root: A Case Study in Design by Principled Optimization
Theorem proving techniques are particularly well suited for reasoning about arithmetic above the bit level and for relating di erent f abstraction. In this paper we show how a non-...
John W. O'Leary, Miriam Leeser, Jason Hickey, Mark...
92
Voted
ICCAD
2004
IEEE
114views Hardware» more  ICCAD 2004»
15 years 11 months ago
Simultaneous short-path and long-path timing optimization for FPGAs
This paper presents the Routing Cost Valleys (RCV) algorithm – the first published algorithm that simultaneously optimizes all short- and long-path timing constraints in a Field...
Ryan Fung, Vaughn Betz, William Chow
123
Voted
ENTCS
2007
85views more  ENTCS 2007»
15 years 2 months ago
Inducing Constructor Systems from Example-Terms by Detecting Syntactical Regularities
We present a technique for inducing functional programs from few, well chosen input/output-examples (I/Oexamples). Potential applications for automatic program or algorithm induct...
Emanuel Kitzelmann, Ute Schmid