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EUROSYS
2010
ACM
15 years 11 months ago
A Comprehensive Scheduler for Asymmetric Multicore Systems
Symmetric-ISA (instruction set architecture) asymmetricperformance multicore processors were shown to deliver higher performance per watt and area for codes with diverse architect...
Juan Carlos Saez, Manuel Prieto Matias, Alexandra ...
ICCD
2006
IEEE
117views Hardware» more  ICCD 2006»
15 years 10 months ago
Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses
— The influence of interconnects on processor performance and cost is becoming increasingly pronounced with technology scaling. In this paper, we present a fast compression sche...
Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Maha...
ICCAD
2008
IEEE
122views Hardware» more  ICCAD 2008»
15 years 10 months ago
Network flow-based power optimization under timing constraints in MSV-driven floorplanning
Abstract— Power consumption has become a crucial problem in modern circuit design. Multiple Supply Voltage (MSV) design is introduced to provide higher flexibility in controllin...
Qiang Ma, Evangeline F. Y. Young
CVPR
2010
IEEE
1208views Computer Vision» more  CVPR 2010»
15 years 10 months ago
Visual Tracking Decomposition
We propose a novel tracking algorithm that can work robustly in a challenging scenario such that several kinds of appearance and motion changes of an object occur at the same time....
Junseok Kwon (Seoul National University), Kyoung M...
ASPLOS
2010
ACM
15 years 8 months ago
ConMem: detecting severe concurrency bugs through an effect-oriented approach
Multicore technology is making concurrent programs increasingly pervasive. Unfortunately, it is difficult to deliver reliable concurrent programs, because of the huge and non-det...
Wei Zhang, Chong Sun, Shan Lu
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