Sciweavers

304 search results - page 16 / 61
» An Access Timing Measurement Unit of Embedded Memory
Sort
View
ARVLSI
1997
IEEE
151views VLSI» more  ARVLSI 1997»
15 years 3 months ago
The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors
A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing the memory latency and improving the memory bandwidth. However, a...
Tadaaki Yamauchi, Lance Hammond, Kunle Olukotun
SIGMOD
2007
ACM
149views Database» more  SIGMOD 2007»
15 years 12 months ago
Mobile and embedded databases
Recent advances in device technology and connectivity have paved the way for next generation applications that are data-driven, where data can reside anywhere, can be accessed at ...
Anil Nori
CODES
2005
IEEE
15 years 1 months ago
An efficient direct mapped instruction cache for application-specific embedded systems
Caches may consume half of a microprocessor’s total power and cache misses incur accessing off-chip memory, which is both time consuming and energy costly. Therefore, minimizing...
Chuanjun Zhang
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
15 years 5 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
RTAS
2006
IEEE
15 years 5 months ago
METERG: Measurement-Based End-to-End Performance Estimation Technique in QoS-Capable Multiprocessors
Multiprocessor systems present serious challenges in the design of real-time systems due to the wider variation of execution time of an instruction sequence compared to a uniproce...
Jae W. Lee, Krste Asanovic