26 search results - page 1 / 6 » An Accurate and Efficient Time-Division Parallelization of C... |
108
Voted
ANSS
2007
IEEE
15 years 4 months ago
2007
IEEE
This paper proposes a parallel cycle-accurate microarchitectural simulator which efficiently executes its workload by splitting the simulation process along time-axis into many in...
85
Voted
MICRO
2007
IEEE
15 years 6 months ago
2007
IEEE
This paper describes FAST, a novel simulation methodology that can produce simulators that (i) are orders of magnitude faster than comparable simulators, (ii) are cycleaccurate, (...
126
Voted
NOCS
2007
IEEE
15 years 6 months ago
2007
IEEE
Network-on-Chip (NoC) architectures have a wide variety of parameters that can be adapted to the designer’s requirements. Fast exploration of this parameter space is only possib...
106
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HPCA
2009
IEEE
16 years 24 days ago
2009
IEEE
Decreasing hardware reliability is expected to impede the exploitation of increasing integration projected by Moore's Law. There is much ongoing research on efficient fault t...
101
Voted
CAL
2006
15 years 9 days ago
2006
Abstract-- Cycle accurate simulation has long been the primary tool for micro-architecture design and evaluation. Though accurate, the slow speed often imposes constraints on the e...