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» An Algorithm for Bi-Decomposition of Logic Functions
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ICCAD
2003
IEEE
219views Hardware» more  ICCAD 2003»
15 years 6 months ago
A Min-Cost Flow Based Detailed Router for FPGAs
Routing for FPGAs has been a very challenging problem due to the limitation of routing resources. Although the FPGA routing problem has been researched extensively, most algorithm...
Seokjin Lee, Yongseok Cheon, Martin D. F. Wong
DAC
2009
ACM
15 years 4 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
114
Voted
POPL
2010
ACM
15 years 7 months ago
Higher-Order Multi-Parameter Tree Transducers and Recursion Schemes for Program Verification
We introduce higher-order, multi-parameter, tree transducers (HMTTs, for short), which are kinds of higher-order tree transducers that take input trees and output a (possibly infi...
Naoki Kobayashi, Naoshi Tabuchi, Hiroshi Unno
FPGA
2009
ACM
273views FPGA» more  FPGA 2009»
15 years 4 months ago
A parallel/vectorized double-precision exponential core to accelerate computational science applications
Many natural processes exhibit exponential decay and, consequently, computational scientists make extensive use of e−x in computer simulation experiments. While it is common to ...
Robin Pottathuparambil, Ron Sass
CIE
2007
Springer
15 years 3 months ago
Computational Complexity of Constraint Satisfaction
Abstract. The input to a constraint satisfaction problem (CSP) consists of a set of variables, each with a domain, and constraints between these variables formulated by relations o...
Heribert Vollmer