113 search results - page 2 / 23 » An Efficient Two-Level Partitioning Algorithm for VLSI Circu... |
GLVLSI
2009
IEEE
13 years 10 months ago
2009
IEEE
A methodology is proposed to efficiently estimate the substrate noise generated by large scale aggressor circuits. Small spatial voltage differences within the ground distribution...
CLEIEJ
2010
13 years 3 months ago
2010
A 3D circuit is the stacking of regular 2D circuits. The advances on the fabrication and packaging technologies allowed interconnecting stacked 2D circuits by using 3D vias. Howeve...
DFT
2005
IEEE
13 years 12 months ago
2005
IEEE
The present paper proposes a new method for detecting arbitrary faults in a functional circuit when the set of codewords is limited and known in advance. The method is based on im...
GLVLSI
2005
IEEE
13 years 12 months ago
2005
IEEE
In this paper we develop a theory of equivalence checking (EC) and logic synthesis of circuits with a common specification (CS). We show that two combinational circuits N1, N2 have...
DAC
1997
ACM
13 years 10 months ago
1997
ACM
In this paper, we present a new hypergraph partitioning algorithm that is based on the multilevel paradigm. In the multilevel paradigm, a sequence of successively coarser hypergra...