421 search results - page 18 / 85 » An Intelligent Parallel Loop Scheduling for Parallelizing Co... |
IPPS
2007
IEEE
15 years 3 months ago
2007
IEEE
This paper presents a technique to visualize the communication pattern of a parallel application at different points during its execution. Unlike many existing tools that show the...
MICRO
1997
IEEE
15 years 1 months ago
1997
IEEE
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...
CGO
2007
IEEE
15 years 4 months ago
2007
IEEE
The increasing complexity of hardware features for recent processors makes high performance code generation very challenging. In particular, several optimization targets have to b...
ICPP
2008
IEEE
15 years 4 months ago
2008
IEEE
This paper describes a generalisation of modulo scheduling to parallelise loops for SpMT processors that exploits simultaneously both instruction-level parallelism and thread-leve...
ICPP
1996
IEEE
15 years 1 months ago
1996
IEEE
Tiling exploits temporal reuse carried by an outer loop of a loop nest to enhance cache locality. Loop skewing is typically required to make tiling legal. This restricts parallelis...