421 search results - page 68 / 85 » An Intelligent Parallel Loop Scheduling for Parallelizing Co... |
IPPS
2007
IEEE
15 years 3 months ago
2007
IEEE
The excessive complexity of both machine architectures and applications have made it difficult for compilers to statically model and predict application behavior. This observatio...
101
click to vote
ISHPC
2003
Springer
15 years 2 months ago
2003
Springer
Simultaneous multithreaded processors use shared on-chip caches, which yield better cost-performance ratios. Sharing a cache between simultaneously executing threads causes excessi...
ISCAPDCS
2003
14 years 11 months ago
2003
Many computation-intensive iterative or recursive applications commonly found in digital signal processing and image processing applications can be represented by data-flow graph...
PLDI
1996
ACM
15 years 1 months ago
1996
ACM
High performance compilers increasingly rely on accurate modeling of the machine resources to efficiently exploit the instruction level parallelism of an application. In this pape...
LCTRTS
2007
Springer
15 years 3 months ago
2007
Springer
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...