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» An Interconnect Energy Model Considering Coupling Effects
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GLVLSI
2000
IEEE
145views VLSI» more  GLVLSI 2000»
15 years 2 months ago
CMOS system-on-a-chip voltage scaling beyond 50nm
† The limits on CMOS energy dissipation imposed by subthreshold leakage currents and by wiring capacitance are investigated for CMOS generations beyond 50nm at NTRS projected loc...
Azeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoo...
SLIP
2009
ACM
15 years 4 months ago
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs
Individual dies in 3D integrated circuits are connected using throughsilicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power ...
Dae Hyun Kim, Saibal Mukhopadhyay, Sung Kyu Lim
HPCA
2005
IEEE
15 years 10 months ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob
ICC
2007
IEEE
105views Communications» more  ICC 2007»
15 years 4 months ago
Effects of Channel Models and Rake Receiving Process on UWB-IR System Performance
Abstract— In ultra-wideband impulse radio (UWB-IR) systems, multipath-delayed received pulses may overlap if two consecutive multipaths arrive within less than the pulse duration...
Serhat Erküçük, Dong In Kim, Kyun...
88
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TOG
2008
142views more  TOG 2008»
14 years 9 months ago
Fast animation of turbulence using energy transport and procedural synthesis
We present a novel technique for the animation of turbulent fluids by coupling a procedural turbulence model with a numerical fluid solver to introduce subgrid-scale flow detail. ...
Rahul Narain, Jason Sewall, Mark Carlson, Ming C. ...