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138
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FPL
2009
Springer
132views Hardware» more  FPL 2009»
15 years 5 months ago
Binary Synthesis with multiple memory banks targeting array references
High-Level Synthesis (HLS) is the field of transforming a high-level programming language, such as C, into a register transfer level(RTL) description of the design. In HLS, Binary...
Yosi Ben-Asher, Nadav Rotem
DSD
2004
IEEE
129views Hardware» more  DSD 2004»
15 years 5 months ago
Functional Validation of Programmable Architectures
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
Prabhat Mishra, Nikil D. Dutt
141
Voted
ASPDAC
2008
ACM
134views Hardware» more  ASPDAC 2008»
15 years 3 months ago
Automatic re-coding of reference code into structured and analyzable SoC models
The quality of the input system model has a direct bearing on the effectiveness of the system exploration and synthesis tools. Given a well-structured system model, tools today are...
Pramod Chandraiah, Rainer Dömer
ISCA
1997
IEEE
120views Hardware» more  ISCA 1997»
15 years 6 months ago
Run-Time Adaptive Cache Hierarchy Management via Reference Analysis
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap b...
Teresa L. Johnson, Wen-mei W. Hwu
97
Voted
WSC
2007
15 years 4 months ago
The SISO CSPI PDG standard for commercial off-the-shelf simulation package interoperability reference models
For many years discrete-event simulation has been used to analyze production and logistics problems in manufacturing and defense. Commercial-off-the-shelf Simulation Packages (CSP...
Simon J. E. Taylor, Navonil Mustafee, Steffen Stra...