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ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
15 years 4 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
FCCM
2002
IEEE
171views VLSI» more  FCCM 2002»
15 years 4 months ago
Coarse-Grain Pipelining on Multiple FPGA Architectures
Reconfigurable systems, and in particular, FPGA-based custom computing machines, offer a unique opportunity to define application-specific architectures. These architectures offer...
Heidi E. Ziegler, Byoungro So, Mary W. Hall, Pedro...
SLIP
2006
ACM
15 years 5 months ago
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
— The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable ha...
Jin Guo, Antonis Papanikolaou, Pol Marchal, Franck...
CONEXT
2005
ACM
15 years 1 months ago
Janus: an architecture for flexible access to sensor networks
We present the design and implementation of the Janus1 architecture for providing flexible and lightweight access to sensor network resources from Internet-type networks. Janus p...
Richard Gold
MCS
2006
Springer
14 years 11 months ago
Architectural concepts and Design Patterns for behavior modeling and integration
The design of the control software for complex systems is a difficult task. It requires the modeling, the simulation, the integration and the adaptation of a multitude of intercon...
Jean-Marc Perronne, Laurent Thiry, Bernard Thirion