443 search results - page 8 / 89 » An interconnection architecture for micropayment systems |
DATE
2009
IEEE
15 years 6 months ago
2009
IEEE
Abstract— In many current SoCs, the architectural interface to onchip monitors is ad hoc and inefficient. In this paper, a new architectural approach which advocates the use of a...
165
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IWMM
2011
Springer
14 years 2 months ago
2011
Springer
Multiprocessors based on processors with multiple cores usually include a non-uniform memory architecture (NUMA); even current 2-processor systems with 8 cores exhibit non-uniform...
114
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CAI
2006
Springer
14 years 11 months ago
2006
Springer
MAS is a powerful paradigm in nowadays distributed systems, however its disadvantage is that it lacks the interconnection with semantic web standards such as OWL. The aim of this a...
146
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DATE
2003
IEEE
15 years 5 months ago
2003
IEEE
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-...
CDC
2009
IEEE
15 years 4 months ago
2009
IEEE
— We consider the design of optimal static feedback gains for interconnected systems subject to architectural constraints on the distributed controller. These constraints are in ...