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» An overview of on-chip interconnect variation
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ISQED
2007
IEEE
206views Hardware» more  ISQED 2007»
14 years 5 months ago
Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations
Abstract—A Network-on-Chip (NoC) replaces on-chip communication implemented by point-to-point interconnects in a multi-core environment by a set of shared interconnects connected...
Mosin Mondal, Tamer Ragheb, Xiang Wu, Adnan Aziz, ...
DAC
2001
ACM
14 years 11 months ago
Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
Kaustav Banerjee, Amit Mehrotra
ISCAS
2007
IEEE
158views Hardware» more  ISCAS 2007»
14 years 5 months ago
Adaptive Low/High Voltage Swing CMOS Driver for On-Chip Interconnects
Abstract— This paper reports the design of a high performance, adaptive low/high swing CMOS driver circuit (mj–driver) suitable for driving of global interconnects with large c...
José C. García, Juan A. Montiel-Nels...
DAC
1998
ACM
14 years 11 months ago
Layout Techniques for Minimizing On-Chip Interconnect Self Inductance
Because magnetic e ects have a much longer spatial range than electrostatic e ects, an interconnect line with large inductance will be sensitive to distant variations in interconn...
Yehia Massoud, Steve S. Majors, Tareq Bustami, Jac...
SLIP
2009
ACM
14 years 5 months ago
Prediction of high-performance on-chip global interconnection
Different interconnection structures have been proposed to solve the performance limitation caused by scaling of on-chip global wires. In this paper, we give an overview of curre...
Yulei Zhang, Xiang Hu, Alina Deutsch, A. Ege Engin...