5268 search results - page 351 / 1054 » Analysis of Design Process Dynamics |
164
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CODES
2007
IEEE
15 years 11 months ago
2007
IEEE
Multiple wireless technologies are converging to run on personal handhelds. The plethora of communication standards next to the cost issues of deeper submicron processing require ...
142
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FPL
2009
Springer
15 years 8 months ago
2009
Springer
This paper investigates the challenges of run-time resource management in future coarse-grained network-onreconfigurable-chips (NoRCs). Run-time reconfiguration is a key feature e...
127
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DATE
2007
IEEE
15 years 11 months ago
2007
IEEE
Networks-on-Chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largel...
145
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DATE
2002
IEEE
15 years 10 months ago
2002
IEEE
This paper develops an improved approach for hierarchical functional test generation for complex chips. In order to deal with the increasing complexity of functional test generati...
159
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ICASSP
2007
IEEE
15 years 11 months ago
2007
IEEE
As dynamic connectivity is shown essential for normal brain function and is disrupted in disease, it is critical to develop models for inferring brain effective connectivity from ...