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» Analysis of a reconfigurable network processor
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VLSID
2004
IEEE
107views VLSI» more  VLSID 2004»
16 years 4 days ago
Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture
With increasing demands for high performance by embedded systems, especially by digital signal processing applications, embedded processors must increase available instruction lev...
Sourabh Saluja, Anshul Kumar
78
Voted
SC
2004
ACM
15 years 5 months ago
Analysis and Performance Results of a Molecular Modeling Application on Merrimac
The Merrimac supercomputer uses stream processors and a highradix network to achieve high performance at low cost and low power. The stream architecture matches the capabilities o...
Mattan Erez, Jung Ho Ahn, Ankit Garg, William J. D...
DFT
2006
IEEE
143views VLSI» more  DFT 2006»
15 years 5 months ago
Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC
This paper1 discusses a defect tolerant and energy economized computing array for the DSP plane of a 3-D Heterogeneous System on a Chip. We present the J-platform, which employs c...
Vijay K. Jain, Glenn H. Chapman
LCN
2005
IEEE
15 years 5 months ago
AntiWorm NPU-based Parallel Bloom Filters for TCP/IP Content Processing in Giga-Ethernet LAN
—TCP/IP protocol suite carries most application data in Internet. TCP flow retrieval has more security meanings than the IP packet payload. Hence, monitoring the TCP flow has mor...
Zhen Chen, Chuang Lin, Jia Ni, Dong-Hua Ruan, Bo Z...
ICCCN
2007
IEEE
15 years 6 months ago
Signaling Transport Options in GMPLS Networks: In-band or Out-of-band
—Signaling protocols for GMPLS networks have been standardized and implemented in switch controllers. Most switch vendors allow for signaling messages to be carried over inband s...
Malathi Veeraraghavan, Tao Li