65 search results - page 8 / 13 » Analysis of buffered hybrid structured clock networks |
107
click to vote
SLIP
2009
ACM
15 years 8 months ago
2009
ACM
This paper proposes an efficient method to predict the worst case of voltage violation by multi-domain clock gating in a three-dimensional (3D) on-chip power network considering l...
121
click to vote
3DIC
2009
IEEE
15 years 8 months ago
2009
IEEE
Abstract—In 3DICs heat dissipating devices are stacked directly on top of each other leading to a higher heat density than in a comparable 2D chip. 3D integration also moves the ...
117
click to vote
MICRO
2006
IEEE
15 years 7 months ago
2006
IEEE
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
114
click to vote
UAI
1996
15 years 2 months ago
1996
In this paper we propose a family of algorithms combining treeclustering with conditioning that trade space for time. Such algorithms are useful for reasoning in probabilistic and...
125
click to vote
USS
2010
14 years 11 months ago
2010
Idle port scanning uses side-channel attacks to bounce scans off of a "zombie" host to stealthily scan a victim IP address and determine if a port is open or closed, or ...