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» Analysis of power consumption in VLSI global interconnects
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CODES
1998
IEEE
15 years 1 months ago
A path analysis based partitioning for time constrained embedded systems
The HW/SW partitioning problem addressed in this paper is one of the key steps in the co-design flow of heterogeneous embedded systems. Generally the aim is to provide solutions t...
Luc Bianco, Michel Auguin, Guy Gogniat, Alain Pega...
ASPDAC
2005
ACM
134views Hardware» more  ASPDAC 2005»
15 years 3 months ago
Wire congestion and thermal aware 3D global placement
— The recent popularity of 3D IC technology stems from its enhanced performance capabilities and reduced wirelength. However, wire congestion and thermal issues are exacerbated d...
Karthik Balakrishnan, Vidit Nanda, Siddharth Easwa...
ASPLOS
2008
ACM
14 years 11 months ago
No "power" struggles: coordinated multi-level power management for the data center
Power delivery, electricity consumption, and heat management are becoming key challenges in data center environments. Several past solutions have individually evaluated different ...
Ramya Raghavendra, Parthasarathy Ranganathan, Vani...
71
Voted
ICCAD
2007
IEEE
128views Hardware» more  ICCAD 2007»
15 years 6 months ago
Module assignment for pin-limited designs under the stacked-Vdd paradigm
Abstract— This paper addresses the module assignment problem in pinlimited designs under the stacked-Vdd circuit paradigm. A partition-based algorithm is presented for efficient...
Yong Zhan, Tianpei Zhang, Sachin S. Sapatnekar
DAC
2002
ACM
15 years 10 months ago
Design of a high-throughput low-power IS95 Viterbi decoder
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often ...
Xun Liu, Marios C. Papaefthymiou