111 search results - page 4 / 23 » Analysis of power consumption in VLSI global interconnects |
VTS
2002
IEEE
15 years 2 months ago
2002
IEEE
For deep sub-micron system-on-chips (SoC), interconnects are critical determinants of performance, reliability and power. Buses and long interconnects being susceptible to crossta...
ISCAS
2006
IEEE
15 years 3 months ago
2006
IEEE
Abstract—Design guidelines for resonant H-tree clock distribution networks are presented in this paper. A distributed model of a two-level resonant H-tree structure is described,...
ASAP
2005
IEEE
15 years 3 months ago
2005
IEEE
Users expect future handhelddevices to provide extended multimedia functionality and have long battery life. This type of application imposes heavy constraints on performance and ...
109
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VLSID
2005
IEEE
15 years 10 months ago
2005
IEEE
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
110
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DAC
1997
ACM
15 years 1 months ago
1997
ACM
This paper describes a new design methodology to analyze the on-chip power supply noise for high performance microprocessors. Based on an integrated package-level and chip-level p...