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» Analysis of power consumption in VLSI global interconnects
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SBCCI
2005
ACM
136views VLSI» more  SBCCI 2005»
15 years 3 months ago
Current mask generation: a transistor level security against DPA attacks
The physical implementation of cryptographic algorithms may leak to some attacker security information by the side channel data, as power consumption, timing, temperature or elect...
Daniel Mesquita, Jean-Denis Techer, Lionel Torres,...
78
Voted
ICS
2005
Tsinghua U.
15 years 3 months ago
A performance-conserving approach for reducing peak power consumption in server systems
The combination of increasing component power consumption, a desire for denser systems, and the required performance growth in the face of technology-scaling issues are posing eno...
Wesley M. Felter, Karthick Rajamani, Tom W. Keller...
DAC
1999
ACM
15 years 10 months ago
Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
Yehea I. Ismail, Eby G. Friedman
SAMOS
2004
Springer
15 years 2 months ago
High-Level Energy Estimation for ARM-Based SOCs
In recent years, power consumption has become a critical concern for many VLSI systems. Whereas several case studies demonstrate that technology-, layout-, and gate-level technique...
Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, P...
ISCAS
2006
IEEE
110views Hardware» more  ISCAS 2006»
15 years 3 months ago
Network-on-chip link analysis under power and performance constraints
— This paper analyzes the behavior of interconnects in the highly structured environment of a network-on-chip (NoC). Two distinct classes of wires are considered, namely links be...
Manho Kim, Daewook Kim, Gerald E. Sobelman