111 search results - page 6 / 23 » Analysis of power consumption in VLSI global interconnects |
SLIP
2009
ACM
15 years 8 months ago
2009
ACM
A novel high-level approach for estimating power consumption of global interconnects in data-path oriented designs implemented in FPGAs is presented. The methodology is applied to...
104
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ISLPED
1997
ACM
15 years 6 months ago
1997
ACM
In this paper we present a methodology and techniques for generating cycle-accurate macro-models for RTlevel power analysis. The proposed macro-model predicts not only...
138
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ISLPED
2005
ACM
15 years 7 months ago
2005
ACM
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
109
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ISVLSI
2006
IEEE
15 years 8 months ago
2006
IEEE
This paper investigates the performance and power dissipation of Globally Asynchronous Locally Synchronous (GALS) multi-processor systems. We show that communication loops are a s...
IJCNN
2008
IEEE
15 years 8 months ago
2008
IEEE
Abstract— This paper introduces a novel design of an artificial neural network tailored for wafer-scale integration. The presented VLSI implementation includes continuous-time a...