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ETS
2007
IEEE
94views Hardware» more  ETS 2007»
15 years 8 months ago
An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy
An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. Therefore embedded memories are commonly equipped with spare r...
Philipp Öhler, Sybille Hellebrand, Hans-Joach...
101
Voted
IPPS
2007
IEEE
15 years 8 months ago
Automatic Trace-Based Performance Analysis of Metacomputing Applications
The processing power and memory capacity of independent and heterogeneous parallel machines can be combined to form a single parallel system that is more powerful than any of its ...
Daniel Becker, Felix Wolf, Wolfgang Frings, Markus...
101
Voted
HPCA
2003
IEEE
16 years 2 months ago
A Statistically Rigorous Approach for Improving Simulation Methodology
Due to cost, time, and flexibility constraints, simulators are often used to explore the design space when developing a new processor architecture, as well as when evaluating the ...
Joshua J. Yi, David J. Lilja, Douglas M. Hawkins
ISPA
2004
Springer
15 years 7 months ago
Highly Reliable Linux HPC Clusters: Self-Awareness Approach
Abstract. Current solutions for fault-tolerance in HPC systems focus on dealing with the result of a failure. However, most are unable to handle runtime system configuration change...
Chokchai Leangsuksun, Tong Liu, Yudan Liu, Stephen...
104
Voted
ICIP
2009
IEEE
16 years 2 months ago
Resource Prediction And Quality Control For Parallel Execution Of Heterogeneous Medical Imaging Tasks
We have established a novel control system for combining the parallel execution of deterministic and non-deterministic medical imaging applications on a single platform, sharing t...