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MICRO
2007
IEEE
115views Hardware» more  MICRO 2007»
15 years 6 months ago
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...
Naveen Muralimanohar, Rajeev Balasubramonian, Norm...
ICCS
2009
Springer
15 years 6 months ago
Evaluation of Hierarchical Mesh Reorderings
Irregular and sparse scientific computing programs frequently experience performance losses due to inefficient use of the memory system in most machines. Previous work has shown t...
Michelle Mills Strout, Nissa Osheim, Dave Rostron,...
VLSID
2008
IEEE
138views VLSI» more  VLSID 2008»
16 years 7 days ago
Memory Architecture Exploration Framework for Cache Based Embedded SOC
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
ADL
2000
Springer
284views Digital Library» more  ADL 2000»
15 years 4 months ago
A Boolean Query Processing with a Result Cache in Mediator Systems
A mediator system is a kind of a meta-search engine that provides a seamlessly integrated search service for diverse search engines (collections). Since collections of a mediator ...
Jae-Heon Cheong, Sang-goo Lee
MSS
2003
IEEE
151views Hardware» more  MSS 2003»
15 years 5 months ago
Accurate Modeling of Cache Replacement Policies in a Data Grid
Caching techniques have been used to improve the performance gap of storage hierarchies in computing systems. In data intensive applications that access large data files over wid...
Ekow J. Otoo, Arie Shoshani