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RTSS
2008
IEEE
15 years 5 months ago
WCET Analysis of Multi-level Non-inclusive Set-Associative Instruction Caches
With the advent of increasingly complex hardware in realtime embedded systems (processors with performance enhancing features such as pipelines, cache hierarchy, multiple cores), ...
Damien Hardy, Isabelle Puaut
SBACPAD
2008
IEEE
170views Hardware» more  SBACPAD 2008»
15 years 5 months ago
Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
James Poe, Chang-Burm Cho, Tao Li
SP
2008
IEEE
117views Security Privacy» more  SP 2008»
15 years 5 months ago
Anonymous Networking with Minimum Latency in Multihop Networks
The problem of security against timing based traffic analysis in multihop networks is considered in this work. In particular, the relationship between the level of anonymity prov...
Parvathinathan Venkitasubramaniam, Lang Tong
GLOBECOM
2007
IEEE
15 years 5 months ago
A Cluster-Based Multiuser Cooperative Network
Abstract— A novel cluster-based coherent multi-user (MU) relaying system is proposed, where a number of source/destination pairs communicate concurrently over the same physical c...
Celal Esli, Armin Wittneben
HPDC
2007
IEEE
15 years 5 months ago
Precise and realistic utility functions for user-centric performance analysis of schedulers
Utility functions can be used to represent the value users attach to job completion as a function of turnaround time. Most previous scheduling research used simple synthetic repre...
Cynthia Bailey Lee, Allan Snavely