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DAC
1997
ACM
15 years 4 months ago
Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design
This paper describes a new design methodology to analyze the on-chip power supply noise for high performance microprocessors. Based on an integrated package-level and chip-level p...
Howard H. Chen, David D. Ling
90
Voted
ICMCS
1996
IEEE
104views Multimedia» more  ICMCS 1996»
15 years 4 months ago
Design and Performance Tradeoffs in Clustered Video Servers
In this paper, we investigate the suitability of clustered architectures for designing scalable multimedia servers. Specifically, we evaluate the effects of: (i) architectural des...
Renu Tewari, Rajat Mukherjee, Daniel M. Dias, Harr...
84
Voted
DAC
1996
ACM
15 years 4 months ago
Bit-Level Analysis of an SRT Divider Circuit
Abstract-- It is impractical to verify multiplier or divider circuits entirely at the bit-level using ordered Binary Decision Diagrams (BDDs), because the BDD representations for t...
Randal E. Bryant
DAC
1996
ACM
15 years 4 months ago
iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips
In this paper, we present the rst chip-level electrothermal simulator, iCET. For a given chip layout, packaging material, user-speci ed input signal patterns, and thermal boundar...
Yi-Kan Cheng, Chin-Chi Teng, Abhijit Dharchoudhury...
117
Voted
DAC
1996
ACM
15 years 4 months ago
Efficient Partial Enumeration for Timing Analysis of Asynchronous Systems
-- This paper presents an efficient method for the timing verification of concurrent systems, modeled as labeled Timed Petri nets. The verification problems we consider require us ...
Eric Verlind, Gjalt G. de Jong, Bill Lin