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ISCA
2000
IEEE
111views Hardware» more  ISCA 2000»
15 years 1 months ago
Understanding the backward slices of performance degrading instructions
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
Craig B. Zilles, Gurindar S. Sohi
IPPS
2009
IEEE
15 years 4 months ago
Exploring the multiple-GPU design space
Graphics Processing Units (GPUs) have been growing in popularity due to their impressive processing capabilities, and with general purpose programming languages such as NVIDIA’s...
Dana Schaa, David R. Kaeli
GRID
2005
Springer
15 years 3 months ago
ASKALON: a Grid application development and computing environment
— We present the ASKALON environment whose goal is to simplify the development and execution of workflow applications on the Grid. ASKALON is centered around a set of high-level...
Thomas Fahringer, Radu Prodan, Rubing Duan, France...
PROCEDIA
2010
140views more  PROCEDIA 2010»
14 years 8 months ago
Jaccard Index based availability prediction in enterprise grids
Enterprise Grid enables sharing and aggregation of a set of computing or storage resources connected by enterprise network, but the availability of the resources in this environme...
Mustafizur Rahman 0003, Md. Rafiul Hassan, Rajkuma...
IPPS
2007
IEEE
15 years 3 months ago
Power-Aware Speedup
Power-aware processors operate in various power modes to reduce energy consumption with a corresponding decrease in peak processor throughput. Recent work has shown power-aware cl...
Rong Ge, Kirk W. Cameron