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DATE
2006
IEEE
134views Hardware» more  DATE 2006»
15 years 7 months ago
ASIP-based multiprocessor SoC design for simple and double binary turbo decoding
This paper presents a new multiprocessor platform for high throughput turbo decoding. The proposed platform is based on a new configurable ASIP combined with an efficient memory a...
Olivier Muller, Amer Baghdadi, Michel Jéz&e...
DDECS
2006
IEEE
95views Hardware» more  DDECS 2006»
15 years 7 months ago
Parallel Memory Architecture for Arbitrary Stride Accesses
—Parallel memory modules can be used to increase memory bandwidth and feed a processor with only necessary data. Arbitrary stride access capability with interleaved memories is d...
Eero Aho, Jarno Vanne, Timo D. Hämäl&aum...
SIGARCH
2008
94views more  SIGARCH 2008»
15 years 1 months ago
Optimized on-chip pipelining of memory-intensive computations on the cell BE
Multiprocessors-on-chip, such as the Cell BE processor, regularly suffer from restricted bandwidth to off-chip main memory. We propose to reduce memory bandwidth requirements, and...
Christoph W. Kessler, Jörg Keller
ICIP
2003
IEEE
16 years 3 months ago
On automatic annotation of meeting databases
In this paper, we discuss meetings as an application domain for multimedia content analysis. Meeting databases are a rich data source suitable for a variety of audio, visual and m...
Daniel Gatica-Perez, Hervé Bourlard, Iain M...
HICSS
2008
IEEE
105views Biometrics» more  HICSS 2008»
15 years 8 months ago
Video Content Description Using Fuzzy Spatio-temporal Relations
One of the important aspects in digital video applications is spatial and temporal characteristic. A very little progress has been achieved on spatiotemporal modeling of video dat...
Archana M. Rajurkar, R. C. Joshi, Santanu Chaudhar...