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CODES
2006
IEEE
15 years 5 months ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
ISLPED
2010
ACM
234views Hardware» more  ISLPED 2010»
14 years 9 months ago
Diet SODA: a power-efficient processor for digital cameras
Power has become the most critical design constraint for embedded handheld devices. This paper proposes a power-efficient SIMD architecture, referred to as Diet SODA, for DSP appl...
Sangwon Seo, Ronald G. Dreslinski, Mark Woh, Chait...
EUROPAR
2008
Springer
15 years 1 months ago
MPC: A Unified Parallel Runtime for Clusters of NUMA Machines
Over the last decade, Message Passing Interface (MPI) has become a very successful parallel programming environment for distributed memory architectures such as clusters. However, ...
Marc Pérache, Hervé Jourdren, Raymon...
CCGRID
2006
IEEE
15 years 3 months ago
Building Cyberinfrastructure for Bioinformatics Using Service Oriented Architecture
-- Cyberinfrastructure makes the development and deployment of bioinformatics applications easier by providing the framework and components that may be loosely coupled using servic...
Wilfred W. Li, Sriram Krishnan, Kurt Mueller, Kohe...
HPCA
2005
IEEE
16 years 6 days ago
Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors
Dynamic voltage and frequency scaling (DVFS) is a widely-used method for energy-efficient computing. In this paper, we present a new intra-task online DVFS scheme for multiple clo...
Qiang Wu, Philo Juang, Margaret Martonosi, Douglas...