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» Application mapping for chip multiprocessors
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ASAP
2005
IEEE
104views Hardware» more  ASAP 2005»
15 years 3 months ago
Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application
Users expect future handhelddevices to provide extended multimedia functionality and have long battery life. This type of application imposes heavy constraints on performance and ...
Andy Lambrechts, Praveen Raghavan, Anthony Leroy, ...
IPPS
2006
IEEE
15 years 3 months ago
Reconfigurable communications for image processing applications
: This work tries to reuse programmable communication resources like a Network-on-Chip (NoC) in the acceleration of image applications. We show a mathematical model for the computa...
André Borin Soares, Luigi Carro, Altamiro A...
DAC
2007
ACM
15 years 10 months ago
Efficient Computation of Buffer Capacities for Cyclo-Static Dataflow Graphs
A key step in the design of cyclo-static real-time systems is the determination of buffer capacities. In our multi-processor system, we apply back-pressure, which means that tasks...
Maarten Wiggers, Marco Bekooij, Gerard J. M. Smit
75
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CCGRID
2008
IEEE
15 years 4 months ago
Scheduling Asymmetric Parallelism on a PlayStation3 Cluster
Understanding the potential and implications of asymmetric multi-core processors for cluster computing is necessary, as these processors are rapidly becoming mainstream components...
Filip Blagojevic, Matthew Curtis-Maury, Jae-Seung ...
HPCA
2003
IEEE
15 years 10 months ago
Hierarchical Backoff Locks for Nonuniform Communication Architectures
This paper identifies node affinity as an important property for scalable general-purpose locks. Nonuniform communication architectures (NUCAs), for example CCNUMAs built from a f...
Zoran Radovic, Erik Hagersten