3171 search results - page 227 / 635 » Application of Reduce Order Modeling to Time Parallelization |
110
click to vote
TC
2008
15 years 3 months ago
2008
Component failures and planned component replacements cause changes in the topology and routing paths supplied by the interconnection network of a parallel processor system over ti...
141
click to vote
EUROPAR
2009
Springer
15 years 8 months ago
2009
Springer
This paper addresses the issue of how to meet the strict timing constraints of (soft) real-time virtualized applications while the Virtual Machine (VM) hosting them is undergoing a...
129
click to vote
GECCO
2006
Springer
15 years 7 months ago
2006
Springer
Garbage collection can be a performance bottleneck in large distributed, multi-threaded applications. Applications may produce millions of objects during their lifetimes and may i...
136
click to vote
BCS
2008
15 years 5 months ago
2008
This paper describes a customisable processor designed to accelerate execution of inductive logic programming, targeting advanced field-programmable gate array (FPGA) technology. ...
139
click to vote
ASIACRYPT
2009
Springer
15 years 10 months ago
2009
Springer
We demonstrate how the framework that is used for creating efficient number-theoretic ID and signature schemes can be transferred into the setting of lattices. This results in cons...