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» Application of Reduce Order Modeling to Time Parallelization
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ITC
1996
IEEE
107views Hardware» more  ITC 1996»
15 years 8 months ago
Orthogonal Scan: Low-Overhead Scan for Data Paths
Orthogonal scan paths, which follow the path of the data flow, can be used in data path designs to reduce the test overhead -- area, delay and test application time -- by sharing ...
Robert B. Norwood, Edward J. McCluskey
CLUSTER
2004
IEEE
15 years 8 months ago
FTC-Charm++: an in-memory checkpoint-based fault tolerant runtime for Charm++ and MPI
As high performance clusters continue to grow in size, the mean time between failure shrinks. Thus, the issues of fault tolerance and reliability are becoming one of the challengi...
Gengbin Zheng, Lixia Shi, Laxmikant V. Kalé
CONCUR
2010
Springer
15 years 5 months ago
Modal Logic over Higher Dimensional Automata
Higher dimensional automata (HDA) are a model of concurrency that can express most of the traditional partial order models like Mazurkiewicz traces, pomsets, event structures, or P...
Cristian Prisacariu
GPEM
2008
98views more  GPEM 2008»
15 years 4 months ago
Sporadic model building for efficiency enhancement of the hierarchical BOA
Efficiency enhancement techniques--such as parallelization and hybridization--are among the most important ingredients of practical applications of genetic and evolutionary algori...
Martin Pelikan, Kumara Sastry, David E. Goldberg
AFRICACRYPT
2009
Springer
15 years 11 months ago
Security Analysis of Standard Authentication and Key Agreement Protocols Utilising Timestamps
We propose a generic modelling technique that can be used to extend existing frameworks for theoretical security analysis in order to capture the use of timestamps. We apply this t...
Manuel Barbosa, Pooya Farshim