3171 search results - page 49 / 635 » Application of Reduce Order Modeling to Time Parallelization |
108
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ICDCS
2000
IEEE
15 years 6 months ago
2000
IEEE
In this paper, we propose an approach to flow-unaware admission control, which is combination with an aggregate packet forwarding scheme, improves scalability of networks while g...
106
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IPPS
2007
IEEE
15 years 8 months ago
2007
IEEE
Partially reconfigurable Field-Programmable Gate Arrays (FPGAs) allow parts of the chip to be configured at run-time where each part could hold an independent task. Online place...
191
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HPDC
2008
IEEE
15 years 8 months ago
2008
IEEE
The emergence of heterogeneous many core architectures presents a unique opportunity for delivering order of magnitude performance increases to high performance applications by ma...
IPPS
2000
IEEE
15 years 6 months ago
2000
IEEE
We present a new parallel repartitioning algorithm for adaptive finite-element meshes that significantly reduces the amount of data that needs to move between processors in orde...
131
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TRETS
2010
15 years 10 days ago
2010
s, and abstractions, typically enabling faster development times than with traditional Hardware ion Languages (HDLs). However, programming at a higher level of abstraction is typic...