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» Application of Reduce Order Modeling to Time Parallelization
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99
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HPCA
2008
IEEE
16 years 3 months ago
Address-branch correlation: A novel locality for long-latency hard-to-predict branches
Hard-to-predict branches depending on longlatency cache-misses have been recognized as a major performance obstacle for modern microprocessors. With the widening speed gap between...
Hongliang Gao, Yi Ma, Martin Dimitrov, Huiyang Zho...
ASAP
2003
IEEE
124views Hardware» more  ASAP 2003»
15 years 8 months ago
Arbitrary Bit Permutations in One or Two Cycles
Symmetric-key block ciphers encrypt data, providing data confidentiality over the public Internet. For inter-operability reasons, it is desirable to support a variety of symmetric...
Zhijie Shi, Xiao Yang, Ruby B. Lee
CASES
2003
ACM
15 years 8 months ago
A low-power accelerator for the SPHINX 3 speech recognition system
Accurate real-time speech recognition is not currently possible in the mobile embedded space where the need for natural voice interfaces is clearly important. The continuous natur...
Binu K. Mathew, Al Davis, Zhen Fang
173
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SRDS
1999
IEEE
15 years 7 months ago
Logging and Recovery in Adaptive Software Distributed Shared Memory Systems
Software distributed shared memory (DSM) improves the programmability of message-passing machines and workclusters by providing a shared memory abstract (i.e., a coherent global a...
Angkul Kongmunvattana, Nian-Feng Tzeng
EMSOFT
2005
Springer
15 years 8 months ago
Optimizing inter-processor data locality on embedded chip multiprocessors
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. T...
Guilin Chen, Mahmut T. Kandemir