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» Application of Reduce Order Modeling to Time Parallelization
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ISPASS
2008
IEEE
15 years 8 months ago
Pinpointing and Exploiting Opportunities for Enhancing Data Reuse
—The potential for improving the performance of data-intensive scientific programs by enhancing data reuse in cache is substantial because CPUs are significantly faster than me...
Gabriel Marin, John M. Mellor-Crummey
VEE
2009
ACM
171views Virtualization» more  VEE 2009»
15 years 8 months ago
Dynamic memory balancing for virtual machines
Virtualization essentially enables multiple operating systems and applications to run on one physical computer by multiplexing hardware resources. A key motivation for applying vi...
Weiming Zhao, Zhenlin Wang
ISSTA
2000
ACM
15 years 6 months ago
UML-Based integration testing
Increasing numbers of software developers are using the Unified Modeling Language (UML) and associated visual modeling tools as a basis for the design and implementation of their ...
Jean Hartmann, Claudio Imoberdorf, Michael Meising...
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
15 years 8 months ago
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Power delivery is a growing reliability concern in microprocessors as the industry moves toward feature-rich, powerhungrier designs. To battle the ever-aggravating power consumpti...
Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hs...
SIROCCO
2007
15 years 3 months ago
Fast Periodic Graph Exploration with Constant Memory
We consider the problem of periodic exploration of all nodes in undirected graphs by using a nite state automaton called later a robot. The robot, using a constant number of state...
Leszek Gasieniec, Ralf Klasing, Russell A. Martin,...