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» Application of Reduce Order Modeling to Time Parallelization
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IEEEPACT
2009
IEEE
15 years 27 days ago
ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs
Abstract--Chip-MultiProcessor (CMP) architectures are becoming more and more popular as an alternative to the traditional processors that only extract instruction-level parallelism...
Carlos Luque, Miquel Moretó, Francisco J. C...
ISORC
2005
IEEE
15 years 8 months ago
Model-Checking of Component-Based Event-Driven Real-Time Embedded Software
As complexity of real-time embedded software grows, it is desirable to use formal verification techniques to achieve a high level of assurance. We discuss application of model-ch...
Zonghua Gu, Kang G. Shin
ISOLA
2004
Springer
15 years 8 months ago
Embedding Finite Automata within regular Expressions
Abstract. Regular expressions and their extensions have become a major component of industry-standard specification languages such as PSL/Sugar ([2]). The model checking procedure...
Shoham Ben-David, Dana Fisman, Sitvanit Ruah
PPOPP
2006
ACM
15 years 9 months ago
Minimizing execution time in MPI programs on an energy-constrained, power-scalable cluster
Recently, the high-performance computing community has realized that power is a performance-limiting factor. One reason for this is that supercomputing centers have limited power ...
Robert Springer, David K. Lowenthal, Barry Rountre...
GLOBECOM
2010
IEEE
15 years 1 months ago
Independent Parallel Compact Finite Automatons for Accelerating Multi-String Matching
Multi-string matching is a key technique for implementing network security applications like Network Intrusion Detection Systems (NIDS) and anti-virus scanners. Existing DFA-based ...
Yi Tang, Junchen Jiang, Xiaofei Wang, Bin Liu, Yan...