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126
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GLVLSI
2006
IEEE
95views VLSI» more  GLVLSI 2006»
15 years 9 months ago
Test generation using SAT-based bounded model checking for validation of pipelined processors
Functional verification is one of the major bottlenecks in microprocessor design. Simulation-based techniques are the most widely used form of processor verification. Efficient ...
Heon-Mo Koo, Prabhat Mishra
119
Voted
CEC
2005
IEEE
15 years 9 months ago
Dynamic power minimization during combinational circuit testing as a traveling salesman problem
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume sig...
Artem Sokolov, Alodeep Sanyal, L. Darrell Whitley,...
145
Voted
SEFM
2005
IEEE
15 years 9 months ago
Experimental Evaluation of FSM-Based Testing Methods
The development of test cases is an important issue for testing software, communication protocols and other reactive systems. A number of methods are known for the development of ...
Rita Dorofeeva, Nina Yevtushenko, Khaled El-Fakih,...
119
Voted
APAQS
2000
IEEE
15 years 8 months ago
Testing for Imperfect Integration of Legacy Software Components
In the manufacturing domain, few new distributed systems are built ground-up; most contain wrapped legacy components. While the legacy components themselves are already well-teste...
David Flater
DATE
2000
IEEE
121views Hardware» more  DATE 2000»
15 years 8 months ago
Functional Test Generation for Full Scan Circuits
We study the effectiveness of functional tests for full scan circuits. Functional tests are important for design validation, and they potentially have a high defect coverage indep...
Irith Pomeranz, Sudhakar M. Reddy