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» Applying Decay to Reduce Dynamic Power in Set-Associative Ca...
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IPPS
2007
IEEE
14 years 20 days ago
Leakage Energy Reduction in Value Predictors through Static Decay
As process technology advances toward deep submicron (below 90nm), static power becomes a new challenge to address for energy-efficient high performance processors, especially for...
Juan M. Cebrian, Juan L. Aragón, José...
CF
2005
ACM
13 years 8 months ago
Drowsy region-based caches: minimizing both dynamic and static power dissipation
Power consumption within the memory hierarchy grows in importance as on-chip data caches occupy increasingly greater die area. Among dynamic power conservation schemes, horizontal...
Michael J. Geiger, Sally A. McKee, Gary S. Tyson
IEEEPACT
2002
IEEE
13 years 11 months ago
Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power
Energy efficiency in microarchitectures has become a necessity. Significant dynamic energy savings can be realized for adaptive storage structures such as caches, issue queues, ...
Steve Dropsho, Alper Buyuktosunoglu, Rajeev Balasu...
ICS
2009
Tsinghua U.
13 years 11 months ago
Dynamic task set partitioning based on balancing memory requirements to reduce power consumption
ABSTRACT Because of technology advances power consumption has emerged up as an important design issue in modern high-performance microprocessors. As a consequence, research on redu...
Diana Bautista, Julio Sahuquillo, Houcine Hassan, ...
CF
2005
ACM
13 years 8 months ago
Controlling leakage power with the replacement policy in slumberous caches
As technology scales down at an exponential rate, leakage power is fast becoming the dominant component of the total power budget. A large share of the total leakage power is diss...
Nasir Mohyuddin, Rashed Bhatti, Michel Dubois