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» Architectural Support for Dynamic Linking
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ICCD
2003
IEEE
167views Hardware» more  ICCD 2003»
15 years 7 months ago
Virtual Page Tag Reduction for Low-power TLBs
We present a methodology for a power-optimized, software-controlled Translation Lookaside Buffer (TLB) organization. A highly reduced number of Virtual Page Number (VPN) bits sufï...
Peter Petrov, Alex Orailoglu
ISORC
2006
IEEE
15 years 5 months ago
An Infrastructure for Adaptive Fault Tolerance on FT-CORBA
The fault tolerance provided by FT-CORBA is basically static, that is, once the fault tolerance properties of a group of replicated processes defined, they cannot be modified in r...
Lau Cheuk Lung, Fábio Favarim, Giuliana Tei...
MICRO
1991
IEEE
85views Hardware» more  MICRO 1991»
15 years 2 months ago
Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors
This paper examines two alternative approaches to supporting code scheduling for multiple-instruction-issue processors. One is to provide a set of non-trapping instructions so tha...
Pohua P. Chang, William Y. Chen, Scott A. Mahlke, ...
DAC
2002
ACM
15 years 12 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...
CODES
2007
IEEE
15 years 5 months ago
Thread warping: a framework for dynamic synthesis of thread accelerators
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circ...
Greg Stitt, Frank Vahid