312 search results - page 32 / 63 » Architectural approaches to reduce leakage energy in caches |
LCTRTS
2007
Springer
15 years 6 months ago
2007
Springer
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
104
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WMPI
2004
ACM
15 years 5 months ago
2004
ACM
In order to meet the requirements concerning both performance and energy consumption in embedded systems, new memory architectures are being introduced. Beside the well-known use o...
118
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ICCAD
2003
IEEE
15 years 8 months ago
2003
IEEE
Abstract— Dynamic voltage scaling (DVS) is a powerful technique for reducing dynamic power consumption in a computing system. However, as technology feature size continues to sca...
120
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HPCA
2009
IEEE
16 years 11 days ago
2009
IEEE
Software cache-based side channel attacks present serious threats to modern computer systems. Using caches as a side channel, these attacks are able to derive secret keys used in ...
IPPS
2007
IEEE
15 years 6 months ago
2007
IEEE
— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with large...