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» Architectural approaches to reduce leakage energy in caches
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IJES
2007
79views more  IJES 2007»
14 years 11 months ago
Energy-aware compilation and hardware design for VLIW embedded systems
Abstract: Tomorrow’s embedded devices need to run high-resolution multimedia applications which need an enormous computational complexity with a very low energy consumption const...
José L. Ayala, Marisa López-Vallejo,...
SENSYS
2005
ACM
15 years 5 months ago
Intelligent light control using sensor networks
Increasing user comfort and reducing operation costs have always been two primary objectives of building operations and control strategies. Current building control strategies are...
Vipul Singhvi, Andreas Krause, Carlos Guestrin, Ja...
EUROMICRO
1999
IEEE
15 years 4 months ago
A Selective Compressed Memory System by On-Line Data Decompressing
This research proposes a selective compressed memory system (SCMS) focusing on a compressed cache architecture, in which only data blocks with good compression efficiency are comp...
Jang-Soo Lee, Won-Kee Hong, Shin-Dug Kim
DAC
2004
ACM
16 years 22 days ago
Multi-profile based code compression
Code compression has been shown to be an effective technique to reduce code size in memory constrained embedded systems. It has also been used as a way to increase cache hit ratio...
Eduardo Wanderley Netto, Rodolfo Azevedo, Paulo Ce...
ASPDAC
2012
ACM
334views Hardware» more  ASPDAC 2012»
13 years 7 months ago
GreenDroid: An architecture for the Dark Silicon Age
— The Dark Silicon Age kicked off with the transition to multicore and will be characterized by a wild chase for seemingly ever-more insane architectural designs. At the heart o...
Nathan Goulding-Hotta, Jack Sampson, Qiaoshi Zheng...